Programmable logic devices are hardware devices whose circuitry can be reconfigured after being manufactured. Programmable logic devices typically include one or more integrated circuits (ICs) that can be integrated into a larger overall system.
A programmable logic device can be reconfigured by writing configuration data into internal configuration memory that defines how programmable elements of the device should function. For example, an FPGA typically includes an array of programmable tiles. These programmable tiles may include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, and delay lock loops (DLLs), to name just a few examples. Another type of programmable logic device is a complex programmable logic device, or CPLD. A CPLD includes two or more “function blocks” connected together and connected to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in programmable logic arrays (PLAs) and programmable array logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
Partially reconfigurable devices (PRDs) are programmable logic devices that allow a portion of the circuitry to be reconfigured while other portions of the circuitry continue to operate according to a previous configuration. PRDs provide the ability to rapidly adapt the configuration of the device in applications where low-latency reactions are important. Such applications include image processing, wireless networking, information retrieval, telecommunications, flight controls, and robotics.
The functionality of a PRD is controlled by data bits written to a configuration space of the device from external memory. Naturally, the speed at which the partial reconfiguration data can be read from the external memory is one of the biggest limiting factors for how quickly a PRD can be reconfigured.